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Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp. Customer Support Dept. April 1, 2003
Cautions
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HN58X2532I/HN58X2564I
Serial Peripheral Interface 32k EEPROM (4-kword x 8-bit) 64k EEPROM (8-kword x 8-bit) Electrically Erasable and Programmable Read Only Memory
ADE-203-1383 (Z) Preliminary Rev. 0.0 Mar. 6, 2003 Description
HN58X25xxx Series is the Serial Peripheral Interface (SPI) EEPROM (Electrically Erasable and Programmable ROM). It realizes high speed, low power consumption and a high level of reliability by employing advanced MONOS memory technology and CMOS process and low voltage circuitry technology. It also has a 32-byte page programming function to make it's write operation faster. Note: Hitachi's serial EEPROM are authorized for using consumer applications such as cellular phones, camcorders, audio equipments. Therefore, please contact Hitachi's sales office before using industrial applications such as automotive systems, embedded controllers, and meters.
Features
* Single supply: 1.8 V to 3.6 V * Serial peripheral interface (SPI bus) SPI mode 0 (0,0), 3 (1,1) * Clock frequency: 5 MHz (2.5 V to 3.6 V), 3 MHz (1.8 V to 3.6 V) * Power dissipation: Standby: 3 A (max) Active (Read): 2.0 mA (max) Active (Write): 2.0 mA (max) * Automatic page write: 32-byte/page * Write cycle time: 5 ms (2.5 V min), 8 ms (1.8 V min) * Endurance: 10 Cycles
5
* Data retention: 10 Years
Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Hitachi's Sales Dept. regarding specifications.
HN58X2532I/HN58X2564I
* Small size packages: SOP-8pin, TSSOP-8pin, and SON-8pin * Shipping tape and reel TSSOP-8pin SOP-8pin SON-8pin : 3,000 IC/reel : 2,500 IC/reel : 3,000 IC/reel
* Temperature range: -40 to +85 C
Ordering Information
Type No. HN58X2532FPI HN58X2564FPI HN58X2532TI HN58X2564TI HN58X2532NI HN58X2564NI Internal organization 32-kbit (4096 x 8-bit) 64-kbit (8192 x 8-bit) 32-kbit (4096 x 8-bit) 64-kbit (8192 x 8-bit) 32-kbit (4096 x 8-bit) 64-kbit (8192 x 8-bit) 1.8 V to 3.6 V 1.8 V to 3.6 V Operating voltage Frequency 1.8 V to 3.6 V 5 MHz (2.5 V to 3.6 V) 3 MHz (1.8 V to 3.6 V) 5 MHz (2.5 V to 3.6 V) 3 MHz (1.8 V to 3.6 V) 5 MHz (2.5 V to 3.6 V) 3 MHz (1.8 V to 3.6 V) 8-pin plastic SON (TNP-8DA) 8-pin plastic TSSOP (TTP-8D) Package 150mil 8-pin plastic SOP (FP-8DB)
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Pin Arrangement
8-pin SOP/TSSOP/SON
S
Q
1 2 3 4
8 7 6 5
VCC
HOLD
C D
W
VSS
(Top view)
Pin Description
Pin name C D Q S W HOLD VCC VSS Function Serial clock Serial data input Serial data output Chip select Write protect Hold Supply voltage Ground
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Block Diagram
High voltage generator VCC
Y decoder
C
Control logic
S W HOLD
D Q
Address generator
X decoder
VSS
Memory array
Y-select & Sense amp.
Serial-parallel converter
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Absolute Maximum Ratings
Parameter Supply voltage relative to VSS Input voltage relative to VSS Operating temperature range* Storage temperature range
1
Symbol VCC VIN Topr Tstg
Value -0.6 to + 7.0 -0.5* to +7.0* -40 to +85 -65 to +125
2 3
Unit V V C C
Notes: 1. Including electrical characteristics and data retention. 2. VIN (min): -3.0 V for pulse width 50 ns. 3. Should not exceed VCC + 1.0 V.
DC Operating Conditions
Parameter Supply voltage Input voltage Operating temperature range Symbol VCC VSS VIH VIL Topr Min 1.8 0 VCC x 0.7 -0.3* -40
1
Typ 0
Max 3.6 0 VCC + 0.5* VCC x 0.3 +85
2
Unit V V V V C
Notes: 1. VIN (min): -1.0 V for pulse width 50 ns. 2. VIN (max): VCC + 1.0 V for pulse width 50 ns.
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DC Characteristics
Parameter Input leakage current Output leakage current VCC current Standby Active Symbol ILI ILO ISB ICC1 Min -- -- -- -- Max 2 2 3 2 Unit A A A mA Test conditions VCC = 3.6 V, VIN = 0 to 3.6 V (S, D, C, HOLD, W) VCC = 3.6 V, VOUT = 0 to 3.6 V (Q) VIN = VSS or VCC, VCC = 3.6 V VCC = 3.6 V, Read at 5 MHz VIN = VCC x 0.1/VCC x 0.9 Q = OPEN VCC = 3.6 V, Write at 5 MHz VIN = VCC x 0.1/VCC x 0.9 VCC = 3.6 V, IOL = 2 mA VCC = 2.5 V, IOL = 1.5 mA VCC = 3.6 V, IOL = -2 mA VCC = 2.5 V, IOL = -0.4 mA
ICC2 Output voltage VOL1 VOL2 VOH1 VOH2
-- -- -- VCC x 0.8 VCC x 0.8
2 0.4 0.4 -- --
mA V V V V
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AC Characteristics
Test Conditions * Input pules levels: VIL = VCC x 0.2 VIH = VCC x 0.8 * Input rise and fall time: 10 ns * Input and output timing reference levels: VCC x 0.3, VCC x 0.7 * Output reference levels: VCC x 0.5 * Output load: 100 pF
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(Ta = -40 to +85C, VCC = 2.5 V to 3.6 V)
Parameter Clock frequency S active setup time S not active setup time S deselect time S active hold time S not active hold time Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock high setup time before HOLD active Clock high setup time before HOLD not active Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output low-Z HOLD low to output high-Z Write time Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH tCL tCLCH tCHCL tDVCH tCHDX tHHCH Alt fSCK tCSS1 tCSS2 tCS tCSH -- tCLH tCLL tRC tFC tDSU tDH -- -- -- -- tDIS tV tHO tRO tFO tLZ tHZ tWC Min -- 90 90 90 90 90 90 90 -- -- 20 30 70 40 60 60 -- -- 0 -- -- -- -- -- Max 5 -- -- -- -- -- -- -- 1 1 -- -- -- -- -- -- 100 70 -- 50 50 50 100 5 Unit MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms 2 2 2 2 2 1 1 2 2 Notes
Clock low hold time after HOLD active tHLCH tCHHL tCHHH tSHQZ tCLQV tCLQX tQLQH tQHQL tHHQX tHLQZ tW
Notes: 1. tCH + tCL 1/fC 2. Value guaranteed by characterization, not 100% tested in production.
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(Ta = -40 to +85C, VCC = 1.8 V to 3.6 V)
Parameter Clock frequency S active setup time S not active setup time S deselect time S active hold time S not active hold time Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock high setup time before HOLD active Clock high setup time before HOLD not active Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output low-Z HOLD low to output high-Z Write time Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH tCL tCLCH tCHCL tDVCH tCHDX tHHCH Alt fSCK tCSS1 tCSS2 tCS tCSH -- tCLH tCLL tRC tFC tDSU tDH -- -- -- -- tDIS tV tHO tRO tFO tLZ tHZ tWC Min -- 100 100 150 100 100 150 150 -- -- 30 50 140 90 120 120 -- -- 0 -- -- -- -- -- Max 3 -- -- -- -- -- -- -- 1 1 -- -- -- -- -- -- 200 120 -- 100 100 100 100 8 Unit MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms 2 2 2 2 2 1 1 2 2 Notes
Clock low hold time after HOLD active tHLCH tCHHL tCHHH tSHQZ tCLQV tCLQX tQLQH tQHQL tHHQX tHLQZ tW
Notes: 1. tCH + tCL 1/fC 2. Value guaranteed by characterization, not 100% tested in production.
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Timing Waveforms
Serial Input Timing
tSHSL
5
tCHSL tSLCH tCHSH
tSHCH
C
tDVCH tCHDX tCLCH LSB IN tCHCL
D
MSB IN
Q
High Impedance
Hold Timing
S
tHLCH tCHHL tHHCH
C
tCHHH
D
tHLQZ tHHQX
Q
HOLD
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Output Timing
5
tCH tSHQZ
C
tCL
D
ADDR LSB IN
tCLQV tCLQX
tCLQX
tCLQV
Q
LSB OUT
tQLQH tQHQL
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Pin Function
Serial data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of serial clock (C). Serial data input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of serial clock (C). Serial clock (C) This input signal provides the timing of the serial interface. Instructions, addresses, or data present at serial data input (D) are latched on the rising edge of serial clock (C). Data on serial data output (Q) changes after the falling edge of serial clock (C). Chip select (S) S When this input signal is high, the device is deselected and serial data output (Q) is at high impedance. Unless an internal write cycle is in progress, the device will be in the standby mode. Driving chip select (S) low enables the device, placing it in the active power mode. After power-up, a falling edge on chip select (S) is required prior to the start of any instruction. HOLD) Hold (HOLD HOLD The hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and serial clock (C) are don't care. To start the hold condition, the device must be selected, with chip select (S) driven low. Write protect (W) W The main purpose of this input signal is to freeze the size of the area of memory that is protected against write instructions (as specified by the values in the BP1 and BP0 bits of the status register). This pin must be driven either high or low, and must be stable during all write operations.
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Functional Description
Status Register The following figure shows the Status Register Format. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. Status Register Format
b7
SRWD 0 0 0 BP1 BP0 WEL
b0
WIP
Status Register Write Protect Block Protect Bits Write Enable Latch Bits Write In Progress Bits
WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the write protect (W) signal. The Status Register Write Disable (SRWD) bit and write protect (W) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits.
Instructions Each instruction starts with a single-byte code, as summarized in the following table . If an invalid instruction is sent (one not contained in the following table), the device automatically deselects itself.
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Instruction Set
Instruction WREN WRDI RDSR WRSR READ WRITE Description Write Enable Write Disable Read Status Register Write Status Register Read from Memory Array Write to Memory Array Instruction Format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010
Write Enable (WREN): The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in the following figure, to send this instruction to the device, chip select (S) is driven low, and the bits of the instruction byte are shifted in, on serial data input (D). The device then enters a wait state. It waits for the device to be deselected, by chip select (S) being driven high. Write Enable (WREN) Sequence
VIH VIL
5 9
VIH VIL 0 1 2 3 4 5 6 7
C
VIH VIL Instruction
D
VIH VIL
Q
High-Z
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Write Disable (WRDI): One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in the following figure, to send this instruction to the device, chip select (S) is driven low, and the bits of the instruction byte are shifted in, on serial data input (D). The device then enters a wait state. It waits for the device to be deselected, by chip select (S) being driven high. The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events: Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion
Write Disable (WRDI) Sequence
VIH VIL
5 9
VIH VIL 0 1 2 3 4 5 6 7
C
VIH VIL Instruction
D
VIH VIL
Q
High-Z
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Read Status Register(RDSR): The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in the following figure. Read Status Register (RDSR) Sequence
VIH VIL
5 9
VIH VIL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
VIH VIL
D
VIH VIL Status Register Out
Q
High-Z 7 6 5 4 3 2 1 0 7
The status and control bits of the Status Register are as follows: WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. When set to 1, such a cycle is in progress. When reset to 0, no such cycles are in progress. WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write Enable Latch is reset and no Write or Write Status Register instructions are accepted. BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits are set to 1, the relevant memory area (as defined in the Status Register Format table) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.
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SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the write protect (W) signal. The Status Register Write Disable (SRWD) bit and write protect (W) signal allows the device to be put in the Hardware Protected mode (When the Status Register Write Disable (SRWD) bit is set to 1, and write protect (W) signal is driven low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Write Status Register (WRSR): The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch(WEL). The instruction sequence is shown in the following figure. The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the Status Register. b6, b5 and b4 are always read as 0. Chip select (S) must be driven high after the rising edge of serial clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (C). Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as chip select (S) is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, Write Enable Latch(WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in the Status Register Format table. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the write protect (W) signal. The Status Register Write Disable (SRWD) bit and write protect (W) signal allows the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0) bits are frozen at their current values just before the start of the execution of the Write Status Register (WRSR) instruction. The new, updated values take effect at the moment of completion of the execution of Write Status Register (WRSR) instruction.
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Write Status Register (WRSR) Sequence
VIH VIL
5 9
VIH VIL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
VIH VIL Status Register In
D
VIH VIL
7 MSB
6
5
4
3
2
1
0
Q
High-Z
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Read from Memory Array (READ): As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The bits of the instruction byte and the address bytes are then shifted in, on serial data input (D). The addresses are loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (Q). If chip select (S) continues to be driven low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can occur at any time during the cycle. The addressed first byte can be any byte within any page. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. Read from Memory Array (READ) Sequence
VIH VIL
5 9
VIH VIL 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C
VIH VIL
Instruction VIH VIL
16-Bit Address
A15 A14 A13 A3 A2 A1 A0
D
Data Out 1
Data Out 2 2 1 0 7
Q
High-Z 7 6 5 4 3
Note:
1. Depending on the memory size, as shown in the following table, the most significant address bits are don't care.
Address Range Bits
Device Address bits HN58X2564I A12 to A0 HN58X2532I A11 to A0
Notes: 1. b15-b13 are don't care on the HN58X2564 2. b15-b12 are don't care on the HN58X2532
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Write to Memory Array (WRITE): As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (D). The instruction is terminated by driving chip select (S) high at a byte boundary of the input data. In the case of the following figure, this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. The self-timed Write cycle starts, and continues for a period tWC (as specified in AC Characteristics). At the end of the cycle, the Write In Progress (WIP) bit is reset to 0. If, though, chip select (S) continues to be driven low, as shown in the following figure, the next byte of the input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal Write cycle. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (The page size of these device is 32 bytes). The instruction is not accepted, and is not executed, under the following conditions: If the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before) If a Write cycle is already in progress If the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
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Byte Write (WRITE) Sequence (1 Byte)
VIH VIL
5 9
VIH VIL 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C
VIH VIL
Instruction VIH VIL
16-Bit Address
Data Byte 1 1 0 7 6 5 4 3 2 1 0
D
15 14 13
3
2
Q
High-Z
Note:
1. Depending on the memory size, as shown in Address Range Bits table, the most significant address bits are don't care.
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Byte Write (WRITE) Sequence (Page)
VIH VIL
5 9
VIH VIL 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C
VIH VIL
Instruction VIH VIL
16-Bit Address
Data Byte 1 1 0 7 6 5 4 3 2 1 0
D
15 14 13
3
2
Q
High-Z
5 9
VIH VIL
VIH VIL 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
VIH VIL
Data Byte 2
Data Byte 3
Data Byte N 1 0 6 5 4 3 2 1 0
D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
Q
High-Z
Note:
1. Depending on the memory size, as shown in Address Range Bits table, the most significant address bits are don't care.
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Data Protect
The protection features of the device are summarized in the following table. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless weather write protect (W) is driven high or low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of write protect (W): If write protect (W) is driven high, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If write protect (W) is driven low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered: By setting the Status Register Write Disable (SRWD) bit after driving write protect (W) low. By driving write protect (W) low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull write protect (W) high. If write protect (W) is permanently tied high, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used.
Write Protected Block Size
Status register bits BP1 0 0 1 1 BP0 0 1 0 1 Protected blocks None Upper quarter Upper half Whole memory Array addresses protected HN58X2564I None 1800h - 1FFFh 1000h - 1FFFh 0000h - 1FFFh HN58X2532I None 0C00h - 0FFFh 0800h - 0FFFh 0000h - 0FFFh
Rev.0.0, Mar. 2003, page 23 of 31
HN58X2532I/HN58X2564I
Protection Modes
Memory protect W signal 1 SRWD bit 0 Mode Software protected (SPM) Write protection of the status register Protected area*
1
Unprotected area* Ready to accept Write instructions
1
Status register is Write protected writable (if the WREN) instruction has set the WEL bit). The values in the BP1 and BP0 bits can be changed.
0 1 0
0 1 1 Hardware protected (HPM) Status register is Write protected hardware write protected. The values in the BP1 and BP0 bits cannot be changed. Ready to accept Write instructions
Note:
1. As defined by the values in the Block Protected (BP1, BP0) bits of the Status Register, as shown in the former table.
Rev.0.0, Mar. 2003, page 24 of 31
HN58X2532I/HN58X2564I
Hold Condition
The hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and serial clock (C) are don't care. To enter the hold condition, the device must be selected, with chip select (S) low. Normally, the device is kept selected, for the whole duration of the hold condition. Deselecting the device while it is in the hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The hold condition starts when the hold (HOLD) signal is driven low at the same time as serial clock (C) already being low (as shown in the following figure). The hold condition ends when the hold (HOLD) signal is driven high at the same time as serial clock (C) already being low. The following figure also shows what happens if the rising and falling edges are not timed to coincide with serial clock (C) being low. Hold Condition Activation
HOLD status HOLD status
C
HOLD
Rev.0.0, Mar. 2003, page 25 of 31
HN58X2532I/HN58X2564I
Notes
Data Protection at VCC On/Off When VCC is turned on or off, noise on S inputs generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this EEPROM have a power on reset function. Be careful of the notices described below in order for the power on reset function to operate correctly. * S should be fixed to VCC during VCC on/off. Low to high or high to low transition during VCC on/off may cause the trigger for the unintentional programming. * VCC should be turned on/off after the EEPROM is placed in a standby state. * VCC should be turned on from the ground level (VSS) in order for the EEPROM not to enter the unintentional programming mode. * VCC turn on speed should be slower than 10 s/V. * When WRSR or WRITE instruction is executed before VCC turns off, VCC should be turned off after waiting write cycle time (tW).
Rev.0.0, Mar. 2003, page 26 of 31
HN58X2532I/HN58X2564I
Package Dimensions
HN58X2532FPI/HN58X2564FPI (FP-8DB)
As of July, 2002
Unit: mm
4.89 5.15 Max 5 8
1
4
3.90 1.73 Max
0.034 *0.22 + 0.017 - 0.20 0.03
6.02 0.18 1.06
0.69 Max
0 - 8
0.114 0.14 + 0.038 -
1.27 *0.42 +0.063 -0.064 0.40 0.06
0.60 - 0.194
+ 0.289
0.10 0.25 M
Hitachi Code JEDEC JEITA Mass (reference value) FP-8DB -- -- 0.08 g
*Dimension including the plating thickness Base material dimension
Rev.0.0, Mar. 2003, page 27 of 31
HN58X2532I/HN58X2564I
HN58X2532TI/HN58X2564TI (TTP-8D)
As of January, 2002
Unit: mm
3.00 3.30 Max 8 5
1 *0.22 +0.08 -0.07 0.20 0.06
4 0.65 1.0 0.13 M 6.40 0.20 0.805 Max 0 - 8 0.50 0.10
4.40
*0.17 0.05 0.15 0.04
1.10 Max
0.10
0.07 +0.03 -0.04
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC JEITA Mass (reference value)
TTP-8D -- -- --
Rev.0.0, Mar. 2003, page 28 of 31
HN58X2532I/HN58X2564I
HN58X2532NI/HN58X2564NI (TNP-8DA)
Unit: mm
3.00 3.10 Max 0.22 - 0.07
+ 0.08
3.60
*0.18 0.05 0.16 0.025
0.80 Max
0.675 Max
*0.145 - 0.045 0.125 0.02
4.06 0.1
+ 0.055
0.65
0.10 0.08 M
0.23
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC JEITA Mass (reference value)
TNP-8DA -- -- 0.022 g
Rev.0.0, Mar. 2003, page 29 of 31
HN58X2532I/HN58X2564I
Disclaimer
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Sales Offices
Hitachi, Ltd.
Semiconductor & Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109
URL
http://www.hitachisemiconductor.com/
For further information write to:
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Europe GmbH Electronic Components Group Dornacher Str 3 D-85622 Feldkirchen Postfach 201, D-85619 Feldkirchen Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay #20-00 Singapore 049318 Tel : <65>-6538-6533/6538-8577 Fax : <65>-6538-6933/6538-3877 URL : http://semiconductor.hitachi.com.sg Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://semiconductor.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-2735-9218 Fax : <852>-2730-0281 URL : http://semiconductor.hitachi.com.hk
Copyright (c) Hitachi, Ltd., 2002. All rights reserved. Printed in Japan.
Colophon 7.0
Rev.0.0, Mar. 2003, page 30 of 31

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